CoreGen is an integrated infrastructure that utilizes traditional compiler techniques to build and verify complex SoC designs. It’s essentially a compiler IR for SoC design and verification. CoreGen utilizes an intermediate representation that permits us to:

• Build high-level optimizations and verification of SoC control and data paths
• Build high-level descriptions of complex SoC’s
• Automatically build HDL representations of the SoC
• Automatically build LLVM compiler backend implementations of the SoC and any extensions
• Permits users to quickly and easily extend the SoC using new or existing IP

The result is significant reduction in design, implementation, and verification of complex SoC’s. CoreGen handles the high-level verification and integration of multiple HDL and high-level language constructs for SoC designs. It also integrates the SoC compiler backend generation.
It DOES NOT handle SoC layout (this is process specific), handle MAC generation for specific external interfaces (this is process specific), and handle downstream tool optimization (Verilog/VHDL).

Intermediate Representation (IR)

CoreGen IR is a semi-strict, well formed IR that permits users & tools to construct SoC designs that can be automatically verified by the CoreGen tools. The IR is stored in memory as C++ objects for easy processing while in use. The IR is stored in memory as C++ objects for easy processing while in use. XML is not ideal, but it’s easily human readabale, abstracts the low-level circuit details of the implementation, and is easily portable between machine architectures.

CoreGen IR has multiple predefined modules that can represent unique portions of the architecture:

• SoC’s: Analogous to a "socket" with all the contained cores, cache and modules. It can also be homogeneous or heterogeneous.
• Cores: RISC-V core with an ISA mode, addressing mode and base implementation (Rocket, Zscale, BOOM, etc.)
• Extensions: Register classes, registers, instructions, etc. beyond the base implementation